die sizing in Chinese

• 挤准模

• "die" in Chinese :    n. (pl. dice ) 1.骰子；骰子状物；一粒骰 ...
• "sizing" in Chinese :    n. 胶料；填料；上胶，上浆。
• "sizing die" in Chinese :    精压模; 整形模
• "curring and sizing die" in Chinese :    翻边整形模
• "hole flanging-sizing die" in Chinese :    翻边成形模; 翻孔整形模
• "sizing" in Chinese :    n. 胶料；填料；上胶，上浆。
• "accurate sizing" in Chinese :    精确筛选
• "after sizing" in Chinese :    后施胶
• "air sizing" in Chinese :    风力分级; 风力分粒; 挤塑
• "alkaline sizing" in Chinese :    碱性施胶
• "automatic sizing" in Chinese :    自动测量
• "back sizing" in Chinese :    背面涂胶
• "ball sizing" in Chinese :    钢球挤
• "beater sizing" in Chinese :    打浆机内施胶; 打浆机中上胶; 打浆上胶
• "boiler sizing" in Chinese :    锅炉系列

• No built - in charge pump leads to smaller die size and more cost savings
  无内嵌的供给泵，这样就会带来更袖珍的小片尺寸以及更多的开销节省。
• Citc schottky wafer capability : 14 to 275 mil die size , 0 . 1 to 120a current , 10 to 300v voltage
  Fs8806espl ag - tag famegs ag - tag可提供一个简单容易的对嵌入式系统认证的解决方案。
• The model is not only working perfectly , but also reducing the pin resource , die size and costs . 5
  该模型不仅可以保证功能正确，而且节约了32根管脚资源，进而缩小了芯片面积、降低设计成本。
• Designed and implemented nic with 0 . 35 um very large scale application specified integrated circuit ( asic ) the die size of nic reaches 350k gates and run at 200mhz 4
  设计并实现了网络接口控制器nic 。 nic采用超大规模专用集成电路asic技术实现，芯片规模为35万门，采用0 . 35 m工艺，最高工作频率达到200mhz 。
• The transistor count is 3 . 8 million ; the package is surface mount 240 - pin quad flat pack ( qfp240 ) ; and the die size is 98mm2 ; the most advanced research progress on microprocessor architecture is extensively studied to get technical preparations for microprocessor design
  该处理器目前正在进行后端设计，即将采用0 . 25 mcmos工艺流片，整个处理器的晶体管数目为380万，封装形式是qfp240 ， die面积为98mm ~ 2 。
• The implementation of in - chip clock generator is often based on modern cmos ic process technology which is usually adopted by very large scale digital system . while designing a deep sub - micrometer cmos circuit , delay , power consumption and die size are of the main factors that must be considered
  使用现代深亚微米cmos集成电路工艺制造的内部时钟发生器要综合考虑延时、功耗、面积等各种重要因素，而且经常要针对soc系统的需求设计特殊的电路结构。